1. Field of the Invention
The invention relates to filters implemented in integrated circuits. More particularly, the invention relates to an improvement in the common mode control loop of a gm-C cell circuit. The invention also relates generally to a control circuit for controlling the voltage of an output signal in a second circuit.
2. Description of the Prior Art
Gm-C circuits are widely used to implement tunable, integrated continuous-time filters. Such filters are used in a wide range of products including communication products. For example, in cellular phones, integrated continuous-time filters are used for reconstruction of signals received by the receiver and anti-aliasing of signals to be transmitted.
The basic elements of a gm-C filter are show in FIG. 1. It is an integrator 100 that includes two circuit branches 10a, 100b each including an electronically adjustable transconductor 110 driving an integrating capacitor Ci. The two branches are coupled in parallel between a first voltage source Vdd and a second, lower voltage source, such as ground. Branch 100a includes current source I2 feeding current to the collector of a cascode bipolar transistor Q2 having its emitter connected to the drain of an input NMOS FET device M2. The source of device M2 is coupled to ground. Branch 100b includes current source I1 feeding cascode bipolar device Q1 which is connected in series with MOS FET device M1 is the same manner as devices Q2, M2 in branch 100a. The devices M1, M2 each have a control gate receiving, respectively, an input signal in+, and its inverse, in-. Input devices M1 and M2 operate in their triode regions with a fixed drain-source voltage "Vds", set by the cascodes Q1 and Q2 and the tuning voltage Vtune applied to the bases of the cascode devices Q1, Q2. Under these conditions, the collector currents of devices Q1 and Q2 are to the first order linearly dependent on the respective input voltages (in+,in-) applied to the gates of input devices M1, M2, realizing a linear transconductance. The value of this transconductance can be controlled by adjusting the tuning voltage Vtune, which through cascodes Q1 and Q2, sets the drain-source voltage Vds of the devices M1 and M2. In general, MOSFET's M1, M2 function as variable resistors, controlled by input signals in+, in-. The integrating capacitor Ci converts, or integrates, the current in branches 100a, 100b to avoltage signal, which is output at the respective outputs out+ and out+. Typically, the tuning voltage Vtune is derived on-chip from an input signal with a well-known frequency. This fixes the absolute frequency response of the integrated filter.
The basic circuit of FIG. 1 cannot be practically used unless the common-mode voltage at the output (out-, out+) of the gm-C cell is controlled. One known implementation of a common-mode control circuit is shown in FIG. 2. The common mode control circuit 150 includes sense resistors R1 and R2, which measure the common-mode component of the output voltage across integrating capacitor Ci. A differential pair, formed by bipolar devices Q3 and Q4, serves as a control amplifier. Two voltage buffers VB1 and VB2 are coupled, respectively, between opposite sides of integrating capacitor Ci and the respective resistors R1, R2. The voltage buffers prevent loading of the gm-C cell 100 by the resistors R1 and R2. The common mode control circuit further includes a reference voltage source Vref and a current mirror formed by PMOS FET devices M3, M4, and M5. The current mirror supplies current to the branches 100a, 100b under control of the differential amplifier.
The common mode control circuit 150 operates as follows. The voltage Vcm at the base of bipolar device Q3 represents the common-mode voltage at the output of the integrator 100. The differential pair Q3, Q4 compares voltage Vcm to a reference voltage Vref presented to the base of transistor Q4. When voltage Vcm differs from the voltage Vref, the current through the devices Q3, R3 will differ from the current through the devices Q4, R4. This difference in current drives the current mirror circuit, consisting of PMOS FETs M3, M4 and MS, until the output common-mode voltage Vcm equals Vref. When the voltage Vcm is greater than Vref, the current through transistor Q3 is greater than through transistor Q4. This causes the gate-source voltage of diode M5 to increase, also increasing the gate-source voltage of transistors M3 and M4. Consequently, the current through M3 and M4 will become greater. When the voltage Vcm is less than the voltage Vref, the current through transistor Q4 is greater than that through transistor Q3. This causes the gate-source voltage of diode M5 to decrease, also decreasing the gate-source voltage of transistors M3 and M4. Consequently, the currents through M3 and M4 will become smaller.
High demands are posed on the common-mode feedback loop 150. This is caused by the fact that the two grounded triode-mode devices M1 and M2 of the integrator provide no common-mode rejection of the input signal in+, in-. Common-mode signals are amplified by the same amount as differential-mode signals. Therefore all of the common-mode rejection between the input and the output of the gm-C cell must be generated by the common-mode feedback loop. As will be discussed, for most filter applications the common-mode rejection ratio has to be higher than unity in order for the filter not to latch-up. To achieve this with the circuit of FIG. 2, the gain of the common-mode control loop has to be higher than the differential gain from the input to the output of the Gm-C cell.
Although it is usually not particularly difficult to achieve this high loop gain DC wise, this is not necessarily so AC wise. The high gain of the common-mode feedback loop moves up its OdB frequency, complicating the task of ensuring sufficient phase margin for stability. One compensating measure taken in the prior art circuit of FIG. 2 is supplying a constant portion of the collector currents of transistors Q1 and Q2 by the separate current sources I1 and I2, instead of burdening the current mirror circuit of devices M3-M5 with the task of providing all the current. This helps to keep the currents through devices M3 and M4 small, moving up their parasitic poles.
To illustrate the importance of common-mode rejection for filter applications, FIG. 3 shows a basic resonator circuit built up around two cross-coupled Gm-C cells 200, 210. The inputs 201, 202 and 211, 212 of the two Gm-C cells 200, 210 correspond to the inputs in+, in- of FIG. 2. Similarly, the outputs 203, 204 and 213, 214 correspond to the outputs out-, out+ of the Gm-C cell of FIG. 2. The output 214 of cell 210 is cross-coupled to the input 201 of cell 200 and the inverted output 213 of the cell 210 is cross-coupled to the inverted input 202 of the cell 200. This cross-coupling ensures that for differential-mode signals the polarity of the feedback is negative. For common-mode signals, however, the cross-coupling has no effect, resulting in positive feedback. To guarantee stability of this positive feedback loop, the total common-mode gain has to be lower than one. This condition is satisfied only when each cell 200, 210 provides sufficient common-mode rejection.
Although the prior art circuit of FIG. 2 under normal conditions is capable of delivering adequate common-mode rejection, this situation changes with large signal excursions at the input. In that case, the common-mode control loop can move out of its linear operating region, reducing the open-loop gain to nearly zero.
Unfortunately, this situation is difficult to prevent. The reason is that the two input devices M1 and M2 (see FIG. 2) have their sources tied to ground, and therefore are capable of conducting large amounts of current when their input signals are high. The drain current of each of the devices M1, M2 is limited only by the maximum gate voltage, which equals Vdd. Thus, for example, for a high input signal equal to Vdd at the inputs 211, 212 of the second cell 210, the devices Q1, M1 and Q2, M2 in each branch 100a, 100b (FIG. 2) will tend to draw a large current. Once the drain current in the devices M1, M2 exceeds the maximum current that the common-mode control circuit 150 can provide, PMOS devices M3 and M4 of the current mirror circuit will not be able to pull up the output voltages out- and out+ to their desired common-mode levels, as set by the reference voltage Vref. The result is that the output nodes 213, 214 of cell 210 are pulled all the way down to ground.
Since the outputs of one Gm-C cell drives the inputs of the following Gm-C cell, as indicated by FIG. 3, the inputs 201, 202 of the cell 200 will also be grounded when the outputs 213, 214 of the cell 210 are pulled low, causing the input devices M1, M2 of cell 200 to turn off. This causes a latch-up situation, because the current sources I1 and I2 have no path to ground and will rail the outputs 203, 204 of the cell 200 to Vdd. This high output voltage at outputs 203, 204 in turn enforces the high input condition at inputs 211, 212 of the following Gm-C cell 210. Thus, the high input condition at inputs 211, 212 are latched high if the common-mode control loop is unable to provide sufficient current to keep the common-mode current at the desired level in response to high input signals to one of the Gm-C cells.
The maximum pull-up current of the common-mode control loop 150 in FIG. 2, apart from the current sources I1 and I2, is set by the constant current source "Itcm" of the common-mode control amplifier and the input-output current-ratio of the current mirror M3-M5. Although it is theoretically possible to increase the tail current providing the source and Itcm to such a value that even under worst case conditions the common-mode loop will always be able to source enough current to prevent latch-up, in practice the required current will become unacceptably large.
FIG. 4 shows a known circuit which prevents latch-up by adding inherent common-mode rejection to the path extending from the input of the Gm-C cell to the output. Circuit elements corresponding to those in FIG. 2 have the same legends. Added to the circuit of FIG. 2 is a differential amplifier 175 with a high common-mode rejection. Common-mode rejection is achieved at this point with a differential pair at the input of the amplifier 175. The addition of the differential amplifier 175 dictates the use of two integrating capacitors Ci1, Ci2 instead of the single integrating capacitor Ci of FIG. 2. Both capacitors are connected across the differential amplifier. In this configuration, capacitors Ci1 and Ci2 each must have twice the value of the capacitor Ci in the circuit of FIG. 2 for the circuit of FIG. 4 to achieve the same transfer characteristics as that in FIG. 2.
Although the solution of FIG. 4 prevents latch-up, it also adds to the complexity and size of the circuit. Not only do the components for the differential amplifier 175 have to be added, but also the total capacitance has quadrupled. Furthermore, the current consumption of the added amplifier stretches the usually already-tight power budget of many applications, especially those relying on battery power, such as in mobile phones.